1. Field of the Invention
The present invention relates to read circuitry for a disk head, and in particular relates to phase-adjustment of a divided clock in such a read circuit, so as to avoid race conditions between time of data validity and latching of such data in accordance with the divided clock.
2. Description of the Related Art
Read circuits for a disk head provide an interface between a magnetic disk head and a hard disk controller, so as to provide verified digital parallel data to the hard disk controller. Such read circuits include a time base generator phase-locked to the output of the disk head so as to provide a high frequency clock reference, together with a divider to provide a divided clock signal for use in latching digital data. A generalized block diagram for a conventional read circuit, showing the time base generator and the divider, is shown in FIG. 1.
As shown in FIG. 1, read circuit 1 accepts as input the pre-amp output from pre-amp 2 which amplifies the analog output from disk head 3. Read circuit 1 provides 9-bit digital data 4 to hard disk controller 5, which in turn provides the digital data to computer bus 6. Internally, read circuit 1 includes a time base generator 8 phase-locked to the output of pre-amp 2 so as to provide a high frequency clock signal 9. In addition, divider 10 operates to divide the output from time base generator 8 (such as division by 8, 8xc2xd, or 9) so as to provide a divided clock signal 11. A/D converter 12 converts the analog output from pre-amp 2 into a digital output such as a 6-bit digital output which is provided to detector 14 (such as a Virterbi detector) which outputs a 1-bit digital signal which is a verified digital bit corresponding to the bit stored on the hard disk. A sequence of such 1-bit digital signals is provided to serial-to-parallel data formatter 15, which converts the 1-bit digital serial data into 9-bit parallel data which includes a parity bit. Each of A/D converter 12, detector 14 and data formatter 15 operate in accordance with high frequency clock 9.
The 9-bit parallel data from data formatter 15, shown at reference numeral 16, is provided to latch 17 which latches the data at a timing determined by divided clock 11. The latched parallel data is thereafter provided to hard disk controller 5, as described before.
FIG. 2 is a timing diagram showing the timing of some signals in the FIG. 1 block diagram. (a) is high frequency clock 9, (b) is the 6-bit output of A/D converter 12, (c) is divided clock 11, and (d) shows validity of 9-bit data 16. As shown in FIG. 2, high frequency clock 9, such as a 600 mHz clock, is divided by divider 10 (in this example, a divide-by-eight divider) into divided clock 11. Superimposed on the waveform for divided clock 11 are count numbers showing the count by which divided clock 11 is created.
Superimposed on A/D converter output 13 is a well-known synchronization marker 20 (hereinafter xe2x80x9cSMxe2x80x9d), which follows the equally well-known synchronization field. Upon encountering the synchronization marker, digital data from the disk head immediately follows. Digital data here is indicated by numerals 21, also superimposed on the A/D converter output 13, which indicate the bit number of the data. 9-bit data 16 is valid after eight bits of data have been collected from the disk head and the ninth parity bit has been added by formatter 15, as shown in FIG. 2.
Because of the construction of conventional read circuits, it is possible for a race condition to arise between the timing at which data 16 is valid and the timing when latch 17 latches the data in accordance with the rising edge of divided clock 11. This race condition is depicted at 22 in FIG. 2, and arises primarily for two reasons. First, because time base generator 8 is phase-controlled to lock with data from the disk head, its phase moves, causing a corresponding movement in phase of divided clock 11. Second, because the occurrence of the synchronization field and the synchronization marker is asynchronous with operation of divider 11, divider 11 is never exactly certain of where, in the output of high frequency clock 9, 9-bit data 16 will be valid.
It is an object of the invention to address the foregoing situation, through the provision of a divider whose phase is adjustable in response to detection of the synchronization marker.
In one aspect, the invention is a read circuit which provides multi-bit disk data to a disk controller based on analog data from a disk head. The read circuit includes a high frequency clock, a bit detector synchronized by the high frequency clock to provide single-bit verified digital data corresponding to the analog output of the disk head, a serial-to-parallel data formatter for formatting the single-bit data into parallel data, and a synchronization mark detector for detecting a synchronization mark. The synchronization mark detector can be arranged to detect the synchronization mark based on the single-bit data from the bit detector. A clock generator generates a lower frequency clock from the high frequency clock, such as by dividing the high frequency clock, with the phase of the clock generator being adjustable in response to the synchronization mark detector. A latch operating in response to the adjusted lower frequency clock latches the parallel output from the serial-to-parallel converter, for use by the disk controller.
Preferably, the high frequency clock is phase-locked to the output of the disk head, and further provides synchronization for an A/D converter that provides digital data to the bit detector. In particularly preferred forms, the clock generator, which generates the lower-frequency clock, operates by a reset of a counter which counts the number of pulses from the high frequence clock. The reset is responsive to the synchronization mark detector so as to reset the counter in a situation where a race condition might arise, and so as not to reset the counter in a situation where a race condition surely would not arise.
Because the phase of the clock generator is adjustable in response to a synchronization mark detector, it is possible to adjust the phase such that a race condition with the timing of valid data does not arise.
This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiment thereof in connection with the attached drawings.